ABSTRACT REGISTRATION (SOON)

Welcome to EuroSOI-ULIS 2025!

On behalf of the Steering and Organizational Committee, we are honored to invite you to 11th Joint EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS 2025), which will be held on May 14-16, 2025, in Warsaw, Poland!

The Joint EuroSOI-ULIS Conference has been an annual event since 2013. The past conferences in this series were organized in Athens, Greece (2017); Granada, Spain (2018); Grenoble, France (2019); Caen, France (2020/virtual and 2021); Udine, Italy (2022); Tarragona, Spain (2023); and Athens, Greece (2024). The organizer of next year’s EuroSOI-ULIS conference edition is the Warsaw University of Technology, the best technical University in Poland.

This Conference aims to gather all scientists and engineers working in the field of SOI technology and nanoscale devices in More-Moore, More-Than-Moore, and Beyond CMOS era in an interactive and pleasant forum. One of the key objectives of the Conference is to promote collaboration and partnership between different academia, research, and industry players in the field.

We cordially invite all students and researchers working in the areas related to the Conference’s topics to submit their abstracts, attend the Conference, meet their colleagues, and enjoy the vibrant atmosphere of the Conference, and the city of Warsaw as well.

We count on your presence. See you soon in Warsaw!

Robert Mroczyński, PhD DSc

General Chair

CALL FOR PAPERS

On behalf of the Steering and Organizational Committee, we are honored to invite you to 11th Joint EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS 2025), which will be held on May 14-16, 2025, in Warsaw, Poland! The Conference aims to gather all scientists and engineers working in the field of SOI technology and nanoscale devices in More-Moore, More-Than-Moore, and Beyond CMOS era.

High-quality contributions in the following areas are solicited:

  1. Advanced SOI materials and structures, innovative SOI-like devices.
  2. Alternative transistor architectures (FDSOI, Nanowire, Nanosheet, FinFET, MuGFET, vertical MOSFET, FeFET and TFET, MEMS/NEMS, Beyond-CMOS).
  3. New channel materials for CMOS (strained Si/SOI, SiGe, GeOI, III-V and high mobility materials on insulator, carbon nanotubes, graphene, and other 2D materials).
  4. Nanometer scale devices: technology, characterization techniques, and evaluation metrics for high performance, low power, low standby power, high frequency, and memory applications.
  5. New functionalities and innovative devices in the More-than-Moore domain: nanoelectronic sensors, biosensor devices, memristors, neuromorphic computing devices, quantum computing devices, energy harvesting devices, RF devices, imagers, integrated photonics (on SOI), etc.
  6. Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
  7. CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling; three-dimensional integration of devices and circuits, heterogeneous integration.
  8. Advanced test structures, characterization techniques, parameter extraction, reliability, and variability assessment techniques for new materials and novel devices.

The Scientific Committee will review original 2-page abstracts with illustrations. The accepted contributions will be published as a Book of Extended Abstracts with ISBN. Selected papers will be published in 4-page letters in the special issue of the Solid-State Electronics journal (ELSEVIER). The “Androula Nassiopoulou Best Paper Award” will be attributed by the SINANO Institute, while the ELSEVIER will attribute the “Best Poster Award”.

In addition, an ICOS Workshop will take place on May 12th – 13th 2025 at the CEZAMAT WUT (free registration, specifics to be announced).

Important dates

abstract submission deadline

January 31, 2025

Notification of acceptance

by February 22, 2025

Deadline for the 4-page paper submission to the Special Issue of Solid-State Electronics

To be announced

(in the picture) Maria Salomea Skłodowska-Curie, the first woman to win a Nobel Prize

Abstracts

You can send your abstracts through our online administration system (available soon). Submissions will be open starting December 9th, 2024. Original 2-page abstracts with illustrations will be accepted for review in pdf format. Papers submitted for review should clearly state:

  • the purpose of the work,
  • how and to what extent it advances the state-of-the-art,
  • specific new results and their impact.

The degree to which the paper deals with these issues will affect the paper selection. The most frequent cause of rejection of submitted papers is a lack of new results. Only work not published at the time of the Conference will be considered. The Scientific Committee considers submitting a paper for review and subsequent acceptance as an agreement that the work will not be placed in the public domain before the Conference. The abstract template will be available here at a later time.

Guidelines for accepted contributions

Posters should be printed at maximal A0 size. (84 x 118 cm). To all interested participants, we will provide a poster printing service on-site (free of charge). Panels will be available all the time during the Conference.

Welcome to Warsaw

Warsaw is the capital of Poland and its biggest city. The city was a witness of wars and the Warsaw Uprising during the II World War (in 1944), during which it was almost wholly destroyed. Rebuilt after the war, it has kept its historical atmosphere in the Old Town. Nowadays, Warsaw is Poland’s business center with headquarters of many international companies. The city is divided into 18 districts.

WUT Main Campus is located in the most central district called “Śródmieście”. Each city has a place that is its showcase and a must-see on any trip. In Warsaw, it’s the Old Town, entered on the UNESCO World Heritage List – it’s where the city’s heart has been beating for centuries. However, when you cross the Vistula River and look at the Old Town from a distance, you are struck by how unusual the city’s panorama is – skyscrapers rise above the red roofs of the Old Town. Historical buildings blend in harmoniously with modern architecture, and the city surprises us by revealing its second face.

Airport

Chopin Airport in Warsaw. The website includes an interactive arrival/departure timetable and information on transportation. To reach WUT, take bus line no. 175 or 188 in front of the Airport Exit gates and get off at the METRO POLITECHNIKA stop. When you get off the bus, you need to walk about 950 m to PL. POLITECHNIKI 1. Another way to reach the city centre and the Central Railway Station is to take a train directly from the airport (look here for more information). When you leave the baggage claims area, you must follow colored lines on the floor.

Taxis

We advise you to use official companies only (see below). Outside of Terminal 2 airport, there is a taxi rank. You will find there official taxis waiting to pick up the customers.

  • City Taxi +48 22 848 88 88
  • Wawa Taxi +48 22 333 44 44
  • Ele Taxi +48 22 811 11 11
  • MPT Taxi +48 22 19191
  • Sawa Taxi +48 22 644 44 44
  • Eco Car +48 123456789

There is also Uber, Bolt and FreeNow. Receipts are available.

Railway

To reach WUT from Central Railway Station (CRS), take the tram line no. 10 in front of the CRS and get off at the Pl. POLITECHNIKI stop.

Accommodation

We recommend that participants use portals such as booking.com and Airbnb to look for short-term rentals in Warsaw.

Please ensure to book accommodation with a flexible cancellation policy, as neither the home nor host universities can offer any reimbursements in case of course cancellation.

Basic travel information can be found here:

Committees

Steering Committee

Francis BALESTRA (CROMA, France)
Maryline BAWEDIN (CROMA, France)
Cor CLAEYS (KU-Leuven, Belgium)
Bogdan CRETU (ENSICAEN, France)
Sorin CRISTOLOVEANU (IMEP-LAHC, France)
Panagiotis DIMITRAKIS (DEMOKRITOS, Greece)
Francisco GAMIZ (University of Granada, Spain)
Elena GNANI (University of Bologna, Italy)
Benjamin INIGUEZ (Universitat Rovira i Virgili, Spain)
Joris LACORD (CEA-Leti, France)
Robert MROCZYŃSKI (Warsaw University of Technology, Poland)
Pierpaolo PALESTRI (University of Udine, Italy)
Enrico SANGIORGI (University of Bologna, Italy)
Luca SELMI (University of Modena, Italy)
Viktor SVERDLOV (TU Wien, Austria)

Organizing Committee

Marcin KIELISZCZYK (Warsaw University of Technology, Poland)
Andrzej MAZURAK (Warsaw University of Technology, Poland)
Jakub WALCZAK (Warsaw University of Technology, Poland)
Piotr WIŚNIEWSKI (CEZAMAT, Warsaw University of Technology, Poland)
& Hanna SATER

Technical Program Committee

Francis BALESTRA (CROMA, France)
Maryline BAWEDIN (CROMA, France)
Bogdan CRETU (ENSICAEN, France)
Sorin CRISTOLOVEANU (IMEP-LAHC, France)
Luca DONETTI (University of Granada, Spain)
Panagiotis DIMITRAKIS (DEMOKRITOS, Greece)
Francisco GAMIZ (University of Granada, Spain)
Vihar GEORGIEV (University of Glasgow, UK)
Gerard GHIBAUDO (IMEP Minatec, France)
Farzan GITY (Tyndall Institute Cork, Ireland)
Paschalis GKOUPIDENIS (Max Planck Institute, Germany)
Elena GNANI (University of Bologna, Italy)
Irina IONICA (INP Grenoble, France)
Valeriya KILCHYTSKA (Catholic University of Louvain-la-Neuve, Belgium)
Sungjun KIM (Dongguk University, Korea)
Joris LACORD (CEA-Leti, France)
Carlos MARQUEZ (CITIC, University of Granada, Spain)
Joao Antonio MARTINO (University of Sao Paulo, Brazil)
Robert MROCZYŃSKI (Warsaw University of Technology, Poland)
Pierpaolo PALESTRI (University of Udine, Italy)
Luca PIRRO (Global Foundries, Germany)
Quentin RAFHAY (IMEP Minatec, France)
Jean-Pierre RASKIN (Catholic University of Louvain-la-Neuve, Belgium)
Carlos SAMPEDRO (University of Granada, Spain)
Enrico SANGIORGI (University of Bologna, Italy)
Viktor SVERDLOV (TU Wien, Austria)
Christoforos THEODOROU (IMEP-LAHC, France)
Alexander ZASLAVSKY (Brown University, USA)
Cezar ZOTA (IBM Zurich, Switzerland)

11th JOINT EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON

EUROSOI-ULIS | 2025

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